In the related art, a technique is used to improve efficiency of a charge pump circuit by changing the frequency of a clock signal for driving the charge pump circuit.
FIG. 4 is a block diagram exemplifying a configuration of a step-up circuit in the related art.
For example, the step-up circuit in FIG. 4 is disclosed in Japanese Laid Open Patent Application No. 2000-236657 (below, referred to as “reference 1”).
In the step-up circuit in FIG. 4, a voltage comparison circuit 105 compares a reference voltage with the output voltage Vout of a charge pump circuit 102, and when a SET signal is input to the voltage comparison circuit 105, the voltage comparison circuit 105 sets a FAST signal status and a SLOW signal status depending on the comparison results.
The SET signal is also input to a frequency setting pointer 103, when the FAST signal is at a high level and the SLOW signal is at a low level, each time the SET signal is input, a high level signal among output signals S1 through Sn of the frequency setting pointer 103 shifts from S1 to Sn in order. To the contrary, when the FAST signal is at the low level and the SLOW signal is at the high level, each time the SET signal is input, a high level signal among the output signals S1 through Sn of the frequency setting pointer 103 shifts from Sn to S1 in order.
The output signals S1 through Sn of the frequency setting pointer 103 are input to a selector 101. Further, a clock signal CLK1, and clock signals CLK2 through CLKn, which are signals obtained by dividing the clock signal CLK1 with a divider 104, are also input to the selector 101. Depending on statuses of the output signals S1 through Sn of the frequency setting pointer 103, one of the clock signals CLK1 through CLKn, which signals are input to the selector 101, is selected and is output to the charge pump circuit 102 as a clock signal Cin.
In other words, when the FAST signal is at the high level, each time the SET signal is input, the frequency of the clock signal Cin is increased, and when the SLOW signal is at the high level, each time the SET signal is input, the frequency of the clock signal Cin is decreased.
In the related art, utilizing such a function, when resetting or powering on a system, a clock signal of a highest frequency is used to boost a voltage to a desired value in a time period as short as possible; in a low power consumption mode or a standby state, a clock signal of a lowest frequency is used to sustain the output voltage of the charge pump circuit 102 to be higher than a preset value. Therefore, the current consumption is reduced to be a minimum.
FIG. 5 is a block diagram illustrating another example of the configuration of a step-up circuit in the related art.
For example, the step-up circuit in FIG. 5 is disclosed in Japanese Laid Open Patent Application No. 2000-278937 (below, referred to as “reference 2”).
In the step-up circuit in FIG. 5, an HVcc detection circuit 117 detects a step-up voltage HVcc, compares the detected step-up voltage HVcc with a reference voltage, and outputs a signal corresponding to a difference between the detected step-up voltage HVcc and the reference voltage to a control circuit 118. In response to the input signal, the control circuit 118 outputs a select signal to a selector 112, the select signal being used for selecting a clock signal having a frequency corresponding to the voltage difference between the detected step-up voltage HVcc and the reference voltage.
In addition, the HVcc detection circuit 117 has plural reference voltages which are used for comparison with the detected step-up voltage HVcc; the HVcc detection circuit 117 selects one of the reference voltages through instructions from the control circuit 118 according to system (like a microcomputer) requests or operation modes, and an output voltage HVcc of a charge pump step up circuit 111 is set according to the selected reference voltage. Therefore, by changing the frequency of a clock signal input to the charge pump step up circuit 111, it is possible to set the step-up voltage HVcc to be any value.
Each of the above techniques of the related art, however, is devised for a single charge pump circuit, but is not suitable for clock signals when using plural charge pump circuits; due to this, problems occur when operating the plural charge pump circuits simultaneously. Specifically, when the plural charge pump circuits are put into operation with the same clock signal, because timings of charging flying capacitors from an input power supply device overlap each other, during the charging, the current output from the input power supply device is large. Due to this, the output voltage from the input power supply device decreases for an instant, and this produces spike noise. When the output voltage from the input power supply device is supplied to a circuit of an apparatus, such spike noise may cause malfunction of the apparatus.
In addition, when the output voltage of a PWM switching regulator is used as the input power supply device of the charge pump circuits, if the ON/OFF timing of switching transistors of the switching regulator overlap the timing of charging the flying capacitors from the input power supply device, the above-mentioned spike noise may become a severe problem.